cpu

package
v1.0.0 Latest Latest
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 Go to latest Published: Apr 7, 2018 License: GPL-3.0 Imports: 4 Imported by: 0

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Index

Constants

View Source 
const (
	ZeroPageBeginIdx         = 0x0
	StackBeginIdx            = 0x100
	RamBeginIdx              = 0x200
	RamMirrorBeginIdx        = 0x800
	LowerIORegBeginIdx       = 0x2000
	LowerIORegMirrorBeginIdx = 0x2008
	UpperIORegBeginIdx       = 0x4000
	ExpansionRomBeginIdx     = 0x4020
	SramBeginIdx             = 0x4000
	PrgRomLowerBeginIdx      = 0x8000
	PrgRomUpperBeginIdx      = 0xc000
	RamSize                  = 0x10000
)
View Source 
const (
	PPUCtrl   = 0x2000
	PPUMask   = 0x2001
	PPUStatus = 0x2002
	OAMAddr   = 0x2003
	OAMData   = 0x2004
	PPUScroll = 0x2005
	PPUAddr   = 0x2006
	PPUData   = 0x2007
	OAMDMA    = 0x4014
	Ctrl1     = 0x4016
)
View Source 
const (
	Set   = 1
	Clear = 0
)

Variables

View Source 
var (
	Implied = AddressingMode{
		Name:   "Implied",
		OpsLen: 0,
		Format: func(ops []byte) string { return "" },
		// contains filtered or unexported fields
	}

	Accumulator = AddressingMode{
		Name:   "Accumulator",
		OpsLen: 0,
		Format: func(ops []byte) string { return "A" },
		// contains filtered or unexported fields
	}

	Immediate = AddressingMode{
		Name:   "Immediate",
		OpsLen: 1,
		Format: func(ops []byte) string { return fmt.Sprintf("#$%02x", ops[0]) },
		// contains filtered or unexported fields
	}

	ZeroPage = AddressingMode{
		Name:   "ZeroPage",
		OpsLen: 1,
		Format: func(ops []byte) string { return fmt.Sprintf("$%02x", ops[0]) },
		// contains filtered or unexported fields
	}

	ZeroPageX = AddressingMode{
		Name:   "ZeroPageX",
		OpsLen: 1,
		Format: func(ops []byte) string { return fmt.Sprintf("$%02x, X", ops[0]) },
		// contains filtered or unexported fields
	}

	ZeroPageY = AddressingMode{
		Name:   "ZeroPageY",
		OpsLen: 1,
		Format: func(ops []byte) string { return fmt.Sprintf("$%02x, Y", ops[0]) },
		// contains filtered or unexported fields
	}

	Relative = AddressingMode{
		Name:   "Relative",
		OpsLen: 1,
		Format: func(ops []byte) string { return fmt.Sprintf("$%02x", ops[0]) },
		// contains filtered or unexported fields
	}

	Absolute = AddressingMode{
		Name:   "Absolute",
		OpsLen: 2,
		Format: func(ops []byte) string { return fmt.Sprintf("$%02x%02x", ops[1], ops[0]) },
		// contains filtered or unexported fields
	}

	AbsoluteX = AddressingMode{
		Name:   "AbsoluteX",
		OpsLen: 2,
		Format: func(ops []byte) string { return fmt.Sprintf("$%02x%02x, X", ops[1], ops[0]) },
		// contains filtered or unexported fields
	}

	AbsoluteY = AddressingMode{
		Name:   "AbsoluteY",
		OpsLen: 2,
		Format: func(ops []byte) string { return fmt.Sprintf("$%02x%02x, Y", ops[1], ops[0]) },
		// contains filtered or unexported fields
	}

	Indirect = AddressingMode{
		Name:   "Indirect",
		OpsLen: 2,
		Format: func(ops []byte) string { return fmt.Sprintf("($%02x%02x)", ops[1], ops[0]) },
		// contains filtered or unexported fields
	}

	IndirectX = AddressingMode{
		Name:   "IndirectX",
		OpsLen: 1,
		Format: func(ops []byte) string { return fmt.Sprintf("($%02x, X)", ops[0]) },
		// contains filtered or unexported fields
	}

	IndirectY = AddressingMode{
		Name:   "IndirectY",
		OpsLen: 1,
		Format: func(ops []byte) string { return fmt.Sprintf("($%02x), Y", ops[0]) },
		// contains filtered or unexported fields
	}
)
View Source 
var OpCodes = map[byte]OpCode{}/* 151 elements not displayed */

Functions

func ADC 

func ADC(cpu *CPU, op Operand) (extraCycles int)

ADC - Add Carry A + val + C => A

N Z C I D V v v v - - v

func AND 

func AND(cpu *CPU, op Operand) (extraCycles int)

AND - And with A A & val => A

N Z C I D V v v - - - -

func ASL 

func ASL(cpu *CPU, op Operand) (extraCycles int)

ASL - Shift Left One Bit val[7] -> c val << 1 -> val

N Z C I D V v v v - - -

func BCC 

func BCC(cpu *CPU, op Operand) (extraCycles int)

BCC - Branch Carry Clear C == 0 -> branch

N Z C I D V - - - - - -

func BCS 

func BCS(cpu *CPU, op Operand) (extraCycles int)

BCS - Branch Carry Set C == 1 -> branch

N Z C I D V - - - - - -

func BEQ 

func BEQ(cpu *CPU, op Operand) (extraCycles int)

BEQ - Branch result zero C == 1 -> branch

N Z C I D V - - - - - -

func BIT 

func BIT(cpu *CPU, op Operand) (extraCycles int)

func BMI 

func BMI(cpu *CPU, op Operand) (extraCycles int)

func BNE 

func BNE(cpu *CPU, op Operand) (extraCycles int)

func BPL 

func BPL(cpu *CPU, op Operand) (extraCycles int)

func BRK 

func BRK(cpu *CPU, op Operand) (extraCycles int)

func BVC 

func BVC(cpu *CPU, op Operand) (extraCycles int)

func BVS 

func BVS(cpu *CPU, op Operand) (extraCycles int)

func CLC 

func CLC(cpu *CPU, op Operand) (extraCycles int)

func CLD 

func CLD(cpu *CPU, op Operand) (extraCycles int)

func CLI 

func CLI(cpu *CPU, op Operand) (extraCycles int)

func CLV 

func CLV(cpu *CPU, op Operand) (extraCycles int)

func CMP 

func CMP(cpu *CPU, op Operand) (extraCycles int)

func CPX 

func CPX(cpu *CPU, op Operand) (extraCycles int)

func CPY 

func CPY(cpu *CPU, op Operand) (extraCycles int)

func DEC 

func DEC(cpu *CPU, op Operand) (extraCycles int)

func DEX 

func DEX(cpu *CPU, op Operand) (extraCycles int)

func DEY 

func DEY(cpu *CPU, op Operand) (extraCycles int)

func EOR 

func EOR(cpu *CPU, op Operand) (extraCycles int)

func INC 

func INC(cpu *CPU, op Operand) (extraCycles int)

func INX 

func INX(cpu *CPU, op Operand) (extraCycles int)

func INY 

func INY(cpu *CPU, op Operand) (extraCycles int)

func JMP 

func JMP(cpu *CPU, op Operand) (extraCycles int)

func JSR 

func JSR(cpu *CPU, op Operand) (extraCycles int)

func LDA 

func LDA(cpu *CPU, op Operand) (extraCycles int)

func LDX 

func LDX(cpu *CPU, op Operand) (extraCycles int)

func LDY 

func LDY(cpu *CPU, op Operand) (extraCycles int)

func LSR 

func LSR(cpu *CPU, op Operand) (extraCycles int)

func NOP 

func NOP(cpu *CPU, op Operand) (extraCycles int)

func ORA 

func ORA(cpu *CPU, op Operand) (extraCycles int)

func PHA 

func PHA(cpu *CPU, op Operand) (extraCycles int)

func PHP 

func PHP(cpu *CPU, op Operand) (extraCycles int)

func PLA 

func PLA(cpu *CPU, op Operand) (extraCycles int)

func PLP 

func PLP(cpu *CPU, op Operand) (extraCycles int)

func ROL 

func ROL(cpu *CPU, op Operand) (extraCycles int)

func ROR 

func ROR(cpu *CPU, op Operand) (extraCycles int)

func RTI 

func RTI(cpu *CPU, op Operand) (extraCycles int)

func RTS 

func RTS(cpu *CPU, op Operand) (extraCycles int)

func SBC 

func SBC(cpu *CPU, op Operand) (extraCycles int)

func SEC 

func SEC(cpu *CPU, op Operand) (extraCycles int)

func SED 

func SED(cpu *CPU, op Operand) (extraCycles int)

func SEI 

func SEI(cpu *CPU, op Operand) (extraCycles int)

func STA 

func STA(cpu *CPU, op Operand) (extraCycles int)

func STX 

func STX(cpu *CPU, op Operand) (extraCycles int)

func STY 

func STY(cpu *CPU, op Operand) (extraCycles int)

func TAX 

func TAX(cpu *CPU, op Operand) (extraCycles int)

func TAY 

func TAY(cpu *CPU, op Operand) (extraCycles int)

func TSX 

func TSX(cpu *CPU, op Operand) (extraCycles int)

func TXA 

func TXA(cpu *CPU, op Operand) (extraCycles int)

func TXS 

func TXS(cpu *CPU, op Operand) (extraCycles int)

func TYA 

func TYA(cpu *CPU, op Operand) (extraCycles int)

Types

type AddressingMode 

type AddressingMode struct {
	Name   string
	OpsLen int
	Format func([]byte) string
	// contains filtered or unexported fields
}

AddressingMode defines one of the 2a03's ways of addressing the operands of the different opcodes.

Each addressing mode is responsible of fetching the operands in it's way, and calling the operation with them.

The bool tells whether there needs to be a page boundry check

The addressing mode returns the amount of extra cycles caused by page boundry crossing, if any.

type CPU 

type CPU struct {
	RAM *RAM
	Reg *Regs
	// contains filtered or unexported fields
}

func New 

func New(ram *RAM) *CPU

func (*CPU) ExecNext 

func (cpu *CPU) ExecNext() (cycles int)

func (*CPU) HandleInterupts 

func (cpu *CPU) HandleInterupts()

func (*CPU) IRQ 

func (cpu *CPU) IRQ()

func (*CPU) LoadROM 

func (cpu *CPU) LoadROM(rom *models.ROM)

func (*CPU) NMI 

func (cpu *CPU) NMI()

func (*CPU) Reset 

func (cpu *CPU) Reset()

type ConstOperand 

type ConstOperand struct {
	D byte
}

func (ConstOperand) Read 

func (op ConstOperand) Read() byte

func (ConstOperand) Write 

func (op ConstOperand) Write(d byte) (cycles int)

type NilOperand 

type NilOperand struct{}

func (NilOperand) Read 

func (op NilOperand) Read() byte

func (NilOperand) Write 

func (op NilOperand) Write(d byte) (cycles int)

type OpCode 

type OpCode struct {
	Name string

	Mode AddressingMode
	Oper Operation
	// contains filtered or unexported fields
}

OpCode defines an opcode of the 2a03.

Contains it's textual representation, addressing mode and the operation itself.

The opcode also contains some informaition on the amount of cycles it takes to execute. cycles is the base cycle count, and pageBoundryCheck tells the addressing mode whether a page boundry cross affects it's cycle count

func (OpCode) Exec 

func (op OpCode) Exec(cpu *CPU, ops ...byte) (extraCycles int)

Exec runs the opcode with the given arguments.

It runs it's addressing mode, which in turn fetches the arguments and calls the operation

type Operand 

type Operand interface {
	Read() byte
	Write(byte) int
}

type Operation 

type Operation func(*CPU, Operand) int

Operation defines an operation that the CPU executes in one or more of it's opcodes.

The byte values it received are it's arguments. Arguments can be of any length, depending on the operation. There isn't a gurantee that the operation will check for the correct number of arguments, so make sure that you pass in the correct amount. Note that the args are in the form of pointers to bytes. This is for the operation to be able to write to the arguments too, changing the underlying RAM or Register.

The operation also gets a reference to the cpu so it can test and change the Registers and RAM.

Similar to addressing modes, opcodes too return whether the operation's execution took extra cycles. This happens on the operation level only in branching operations.

type RAM 

type RAM struct {
	CPU  *CPU
	PPU  *ppu.PPU
	Ctrl *models.Controller
	// contains filtered or unexported fields
}

func (*RAM) Observe 

func (r *RAM) Observe(addr int) byte

func (*RAM) Read 

func (r *RAM) Read(addr int) byte

func (*RAM) Write 

func (r *RAM) Write(addr int, d byte) (cycles int)

type RAMOperand 

type RAMOperand struct {
	RAM  *RAM
	Addr int
}

func (RAMOperand) Read 

func (op RAMOperand) Read() byte

func (RAMOperand) Write 

func (op RAMOperand) Write(d byte) (cycles int)

type RegOperand 

type RegOperand struct {
	Reg *byte
}

func (RegOperand) Read 

func (op RegOperand) Read() byte

func (RegOperand) Write 

func (op RegOperand) Write(d byte) (cycles int)

type Regs 

type Regs struct {
	PC int
	SP byte

	A byte
	X byte
	Y byte

	C byte
	Z byte
	I byte
	D byte
	B byte
	V byte
	N byte
}

func (*Regs) GetP 

func (reg *Regs) GetP() byte

func (*Regs) SetP 

func (reg *Regs) SetP(p byte)

type Worker 

type Worker struct {
	// contains filtered or unexported fields
}

func NewWorker 

func NewWorker(rom *models.ROM, disp ppu.Displayer, ctrl *models.Controller) *Worker

func (*Worker) Start 

func (w *Worker) Start()

Source Files

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